Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices
Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices
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DOI：
10.1145/3390771
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发表时间：
2020-07-01
影响因子：
2.2
通讯作者：
Thapliyal, Himanshu
中科院分区：
文献类型：
--
作者：
Kumar, S. Dinesh;Thapliyal, Himanshu
物联网（IoT）设备对功率和能耗有严格的限制。绝热逻辑已被提出作为一种新的计算平台来设计节能的物联网设备。物理不可克隆功能（PUF）是解决诸如集成电路（IC）盗版、IC伪造等安全问题的有前景的范例。PUF已经显示出以廉价的方式产生可以在安全系统中使用的秘密比特的巨大前景。然而，设计一个可靠的PUF沿着与能源效率是一个很大的挑战。因此，为了节能和可靠的PUF，我们提出了一种新的节能绝热逻辑为基础的PUF结构。所提出的绝热PUF使用能量回收概念来实现高能量效率，并且使用时间斜坡电压来展现可靠的启动行为。晶体管的沟道长度在控制制造变化方面起主要作用。因此，在这篇文章中，在Cadence Spectre模拟器中使用180 nm和45 nm互补金属氧化物半导体（CMOS）技术进行电路模拟，以分析沟道长度变化的影响。所提出的绝热PUF在180 nm和45 nm CMOS工艺下分别具有96.84%和99.6%的最坏情况可靠性。此外，所提出的绝热PUF在180 nm CMOS工艺下每周期消耗1.071fJ/比特，在45 nm CMOS工艺下每周期消耗0.08fJ/比特。
Internet of Things (IoT) devices have stringent constraints on power and energy consumption. Adiabatic logic has been proposed as a novel computing platform to design energy-efficient IoT devices. Physically Unclonable Functions (PUFs) is a promising paradigm to solve security concerns such as Integrated Circuit (IC) piracy, IC counterfeiting, and the like. PUFs have shown great promise for generating the secret bits that can be used in the secure systems in an inexpensive way. However, designing a reliable PUF along with energy-efficiency is a big challenge. Therefore, for energy-efficient and reliable PUFs, we are proposing a novel energy-efficient adiabatic logic-based PUF structure. The proposed adiabatic PUF uses energy recovery concept to achieve high energy efficiency and uses the time ramp voltage to exhibit the reliable start-up behavior. The channel length of the transistors play a major role in controlling manufacturing variations. So, in this article, the circuit simulations are performed with 180nm and 45nm Complementary metal-oxide-semiconductor (CMOS) technology in a Cadence Spectre simulator to analyze the impact of channel length variations. The proposed adiabatic PUF has worst-case reliability of 96.84% and 99.6% with temperature variations at 180nm and 45nm CMOS technology, respectively. Further, the proposed adiabatic PUF consumes 1.071fJ/bit-per cycle at 180nm CMOS technology and 0.08fJ/bit-per cycle at 45nm CMOS technology.