An Approximate Carry Estimating Simultaneous Adder with Rectification

An Approximate Carry Estimating Simultaneous Adder with Rectification
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带整流的近似进位估计同步加法器

DOI:
10.1145/3386263.3406928
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发表时间:
2020
期刊:
Proceedings of the 2020 on Great Lakes Symposium on VLSI
影响因子:
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通讯作者:
D. Banerjee
D. Banerjee
中科院分区:
--
文献类型:
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作者:
Rajat Bhattacharjya;Vishesh Mishra;Saurabh Singh;Kaustav Goswami;D. Banerjee

文献摘要

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近似计算近年来在降低算术运算的功耗、面积和时间要求方面有了重要应用。近年来的一些研究工作在这些方向上进一步推动了近似计算的发展。在这项工作中,我们提出了一种新的采用进位预测方法的近似加法器。这使得进位能够并行传播,从而实现更快的计算。除了基本的加法器设计,我们还提出了一种校正逻辑,它能够在更大规模的计算中实现更高的精度。实验结果表明,我们的加法器产生结果的速度比传统的行波进位加法器快91.2%。在精度方面,在基本设计中加入校正逻辑后产生的结果比最先进的加法器(如SARA[13]和BCSA[5])的精度高74%。
Approximate computing has in recent times found significant applications towards lowering power, area, and time requirements for arithmetic operations. Several works done in recent years have furthered approximate computing along these directions. In this work, we propose a new approximate adder that employs a carry prediction method. This allows parallel propagation of the carry allowing faster calculations. In addition to the basic adder design, we also propose a rectification logic which would enable higher accuracy for larger computations. Experimental results show that our adder produces results 91.2% faster than the conventional ripple-carry adder. In terms of accuracy, the addition of rectification logic to the basic design produces results that are more accurate than state-of-the-art adders like SARA[13] and BCSA[5] by 74%.