Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier
Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier
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DOI：
10.1126/science.1220527
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发表时间：
2012-06-01
期刊：
影响因子：
56.9
通讯作者：
Kim, Kinam
中科院分区：
文献类型：
--
作者：
Yang, Heejun;Heo, Jinseong;Kim, Kinam
尽管对石墨烯电子学进行了几年的研究，但在具有常规器件结构的石墨烯晶体管中不可能获得足够的开/关电流比I-on/I-off。我们报道了一种三端有源器件，石墨烯可变势垒“barristor”（GB），其中的关键是石墨烯和氢化硅之间原子级尖锐的界面。通过调节栅极电压以控制石墨烯-硅肖特基势垒来实现对器件电流的大调制（10（5）的开/关比）。在界面处没有费米能级钉扎允许通过调整石墨烯的功函数将势垒的高度调谐到0.2电子伏，这导致二极管阈值电压的大偏移。在各自的150毫米晶圆上制作GB，并结合互补的p型和n型GB，我们演示了反相器和半加法器逻辑电路。
Despite several years of research into graphene electronics, sufficient on/off current ratio I-on/I-off in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.