A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS
A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS
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采用 40nm CMOS 封装的 73μW 400Mbps 耐压 1.8V-3.6V 驱动器
DOI：
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发表时间：
2011
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通讯作者：
Vinod Kumar
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文献类型：
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作者：
Sushrant Monga;Vinod Kumar
提出了一种适用于高电压（3.6V）应用的I/O驱动器结构，该结构使用低压器件。建议的I/O可配置为支持多电源范围（1.8V-2.7V-3.6V）。该缓冲器采用40 nm CMOS工艺设计，采用标准的32 μ m氧化层器件。该技术产生一组动态偏置信号，作为输入数据序列和输出的当前值的函数，其被馈送到级联级以导出输出PAD的下一状态。实验结果证实，在IO焊盘上具有10 pF负载和多个供电轨的情况下，该器件可在高达200 MHz的频率下成功工作。
Architecture for I/O driver is proposed for high voltage (up to 3.6V) application by using low voltage devices. The proposed I/O is configurable to support multi supply range (1.8V-2.7V-3.6V). The buffer is designed in 40nm CMOS process by using standard 32Å oxide devices. This technique generates a set of dynamic bias signals as a function of input data sequence and the present value of the output which are fed to the cascoded stages to derive the next state of the output PAD. The experimental results confirmed successful operation up to 200 MHz with 10pF load on IO pad, with multiple supply rails.