Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack
Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack
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DOI：
10.1109/led.2012.2218565
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发表时间：
2012
影响因子：
4.9
通讯作者：
B. Benbakhti;J. F. Zhang;Z. Ji;W. Zhang;J. Mitard;B. Kaczer;G. Groeseneken;S. Hall;J. Robertson;P. Chalker
中科院分区：
文献类型：
--
作者：
B. Benbakhti;J. F. Zhang;Z. Ji;W. Zhang;J. Mitard;B. Kaczer;G. Groeseneken;S. Hall;J. Robertson;P. Chalker
硅封盖的Ge MOSFET与现有工艺具有良好的兼容性，已有报道取得了令人满意的结果。这一过程正变得足够成熟，足以保证对设备可靠性的评估。观察到了良好的时间相关介电击穿性能，并且负偏压温度不稳定性磁化率好于硅材料。电子陷阱被证明是有问题的，并通过正偏压、温度不稳定性和热载流子注入影响器件。这封信描述了Si-Caped Ge上HfO2/SiO_2堆栈中的电子陷阱。陷阱很大，随着电压的增大而增大，在电压为2.0V时，在100μ的S中达到约1013 cm-2。我们首次通过测量瞬态门电流得到了两个不同的俘获截面。较大的CCS可达~10-12 cm~2，当氧化场较高时，CCS减小，这是库仑吸引中心的特征。小的CCS约为10-14cm2，这是在SiO_2和HfO_2/SiO_2堆栈中发现的电子陷阱的典型数值。
Si-capped Ge MOSFETs have good compatibility with existing processes, and promising results have been reported. The process is becoming sufficiently mature to warrant assessment of device reliability. Good time-dependent dielectric breakdown performance has been observed, and negative-bias-temperature-instability susceptibility is better than Si counterparts. Electron trapping is shown to be problematic and affects devices through positive bias temperature instability and hot carrier injection. This letter characterizes electron trapping in HfO2/SiO2 stacks on Si-capped Ge. Trapping is substantial, increasing with VG and reaching ~ 1013 cm-2 in 100 μs under VG = 2.0 V. We report, for the first time, two distinctive capture cross sections (CCS) by measuring the transient gate current. The large CCS can be ~ 10-12 cm2 and reduces for a higher oxide field, which is a signature of coulombic attractive centers. The small CCS is on the order of 10-14 cm2, which is a typical value found for electron traps in SiO2 and HfO2/SiO2 stacks on Si.