A Probabilistic and Constraint Based Approach for Low Power Test Generation
A Probabilistic and Constraint Based Approach for Low Power Test Generation
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一种基于概率和约束的低功耗测试生成方法
DOI：
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发表时间：
2012
期刊：
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通讯作者：
Z. Navabi
中科院分区：
文献类型：
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作者：
H. Bidgoli;Majid Namaki;Z. Navabi
将扫描链与组合自动测试模式生成 (ATPG) 一起插入电路是数字电路最常用的测试技术。由于测试模式下的功耗通常比功能模式下的功耗高得多，因此在 ATPG 期间应考虑一些因素。本文提出了一种基于概率和约束的方法，用于基于扫描的低功耗测试生成。该 ATPG 利用信号概率分析来估计故障检测概率以及信号转换活动来指导测试生成过程。通过将所提出的方法应用于具有三种不同功率约束（包括传播、捕获和移位）的 ISCAS85 和 ISCAS89 基准，评估了该方法的有效性。
Inserting scan chain into the circuit alongside the combinational automatic test pattern generation (ATPG) is the most commonly used test technique for digital circuits. Since power dissipation in test mode is generally much higher than in the functional mode, some considerations should be made during ATPG. This paper presents a probabilistic and constraint based approach for scan-based low power test generation. This ATPG exploits signal probability analysis to estimate fault detection probability as well as signal transition activities to guide test generation process. The effectiveness of the proposed approach has been evaluated by applying it to ISCAS85 and ISCAS89 benchmarks with three different power constraints, including propagation, capture, and shift.