Mechanistic Modeling of Architectural Vulnerability Factor
Mechanistic Modeling of Architectural Vulnerability Factor
复制标题
建筑脆弱因素的机制建模
DOI：
10.1145/2669364
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
L. Eeckhout
中科院分区：
文献类型：
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作者：
Arun A. Nair;Stijn Eyerman;Jian Chen;L. John;L. Eeckhout
由于芯片上晶体管数量的指数级增长以及每一代工艺的工作电压的降低，软错误的可靠性是现代微处理器中的一个重大设计挑战。使用微架构模拟器进行架构脆弱性因子（AVF）建模，使架构师能够在性能、功耗和可靠性方面做出明智的权衡。然而，这样的模拟器是耗时的，并没有揭示影响AVF的微架构机制。在这篇文章中，我们提出了一个精确的一阶机械分析模型来计算AVF，开发使用的第一原则的顺序超标量执行。该模型提供了对共同影响AVF的工作负载和微架构之间的基本交互的洞察。我们使用该模型来执行设计空间探索，参数扫描，和AVF的工作负载表征。
Reliability to soft errors is a significant design challenge in modern microprocessors owing to an exponential increase in the number of transistors on chip and the reduction in operating voltages with each process generation. Architectural Vulnerability Factor (AVF) modeling using microarchitectural simulators enables architects to make informed performance, power, and reliability tradeoffs. However, such simulators are time-consuming and do not reveal the microarchitectural mechanisms that influence AVF. In this article, we present an accurate first-order mechanistic analytical model to compute AVF, developed using the first principles of an out-of-order superscalar execution. This model provides insight into the fundamental interactions between the workload and microarchitecture that together influence AVF. We use the model to perform design space exploration, parametric sweeps, and workload characterization for AVF.