A multisampling time-domain CMOS imager with synchronous readout circuit
A multisampling time-domain CMOS imager with synchronous readout circuit
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DOI：
10.1007/s10470-008-9194-5
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发表时间：
2008-11-01
影响因子：
1.4
通讯作者：
Swart, Jacobus W.
中科院分区：
文献类型：
--
作者：
Campos, Fernando S.;Marinov, Ognian;Swart, Jacobus W.
提出了一种新的CMOS成像器的同步读出和宽动态范围的多周期时域结构。所提出的multisystem架构只需要一个单一的每像素存储器位，而不是8位，这是典型的时域有源像素架构。目标是获得具有高动态范围的时域成像器，该时域成像器需要每像素较少数量的晶体管以实现较高的填充因子。分析了最大帧速率与位数和数组大小的关系。分析表明，有可能实现高帧速率并在具有10位像素数据分辨率的视频模式下操作。此外，我们提出的比较器失调电压的固定模式噪声的影响进行了分析。该架构实现了在AMS CMOS 0.35 μ m制造的32 × 32像素阵列的成像器原型，其特征在于灵敏度，噪声和颜色响应。像素尺寸为30 μ m × 26 μ m，由一个n+/psub光电二极管、一个比较器和一个填充因子为16%的D触发器组成。
A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 x 32 pixel array fabricated in AMS CMOS 0.35 mu m and was characterized for sensitivity, noise and color response. The pixel size is 30 mu m x 26 mu m and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.