A Design Framework for Invertible Logic
A Design Framework for Invertible Logic
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DOI：
10.1109/ieeeconf44664.2019.9048700
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发表时间：
2019-11
期刊：
影响因子：
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通讯作者：
N. Onizawa;Kaito Nishino;S. C. Smithson;B. Meyer;W. Gross;Hitoshi Yamagata;Hiroyuki Fujita;T. Hanyu
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文献类型：
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作者：
N. Onizawa;Kaito Nishino;S. C. Smithson;B. Meyer;W. Gross;Hitoshi Yamagata;Hiroyuki Fujita;T. Hanyu
最近已经提出了使用概率磁阻器件模型的可逆逻辑，其可以双向方式操作并且快速地解决若干问题，诸如因子分解和组合优化。本文提出了一种大规模可逆逻辑电路的设计框架.我们的方法利用线性规划来创建一个具有最少节点数的Hamilton库。此外，由于在SystemVerilog中基于随机计算来近似器件模型，因此与传统的SPICE级仿真相比，使用编译的SystemC二进制来实现更快的仿真。我们已经评估了我们的框架设计可逆乘数，实现了近5个数量级的速度比传统方法的模拟。
Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can operate in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this paper, we present a design framework for large- scale invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes. In addition, as the device model is approximated based on stochastic computing in SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation. We have evaluated our framework on designing invertible multipliers, which realizes almost 5 order-of-magnitude faster simulation than a conventional method.