A programmable method for low-power scan shift in SoC integrated circuits
A programmable method for low-power scan shift in SoC integrated circuits
复制标题
SoC集成电路中低功耗扫描移位的可编程方法
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
A. Sanghani
中科院分区：
文献类型：
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作者：
Ran Wang;Bonita Bhaskaran;Karthikeyan Natarajan;Ayub Abdollahian;Kaushik Narayanun;K. Chakrabarty;A. Sanghani
提出了一种可编程的移位时钟交错分配方法，以降低片上系统（SoC）测试中的电源噪声。SoC设计通常由若干块组成，并且共享相同电源轨的两个相邻块不应在移位期间同时切换。因此，所提出的可编程方法不向相邻块分配相同的交错值。首先分析所有块的位置，然后计算块之间的共享边界长度。根据块体之间的位置关系，提出了一个数学模型，用于求解中小型问题的最优解。对于较大的设计，提出了一种启发式算法和评估。我们目前的分配结果以及功率分析结果和硅数据的工业设计，以突出所提出的方法的有效性。
We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated. We present assignment results as well as power-analysis results and silicon data for industry designs to highlight the effectiveness of the proposed method.