Sub-5 nm Gate Length Monolayer MoTe2 Transistors
Sub-5 nm Gate Length Monolayer MoTe2 Transistors
复制标题
低于 5 nm 栅极长度单层 MoTe2 晶体管
DOI：
10.1021/acs.jpcc.1c01754
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发表时间：
2021-08-26
影响因子：
3.7
通讯作者：
Lu, Jing
中科院分区：
文献类型：
--
作者：
Li, Qiang;Yang, Jie;Lu, Jing
由于硅基场效应晶体管（FET）正在接近其缩放极限，因此已经提出二维（2D）半导体作为替代沟道材料。最近，空气稳定的二维三层（TL）MoTe2场效应晶体管的栅极长度为4 nm的实验已经制造。为了探索单层MoTe2场效应晶体管的器件性能极限，我们采用量子输运从头算方法模拟了亚5 nm栅长双栅（DG）ML MoTe2场效应晶体管。我们发现，当考虑到负电容技术和欠重叠，3纳米栅极长度的p型DG ML MoTe2 FET的性能可以满足国际技术路线图半导体2013年的要求，在2028年的地平线上的高性能和低功耗应用。因此，ML MoTe 2作为沟道材料可以将摩尔定律缩小到3nm。
Since silicon-based field-effect transistors (FETs) are approaching their scaling limit, two-dimensional (2D) semiconductors have been proposed as alternative channel materials. Recently, air-stable 2D trilayer (TL) MoTe2 FETs with a 4 nm gate length have been fabricated experimentally. To explore the device performance limit of the monolayer MoTe2 FETs, we simulate the sub-5 nm gate length double-gate (DG) ML MoTe2 FETs by using the ab initio quantum transport method. We find that when taking negative capacitance technology and underlap into account, the performances of the 3 nm gate length p-type DG ML MoTe2 FETs can satisfy the International Technology Roadmap for Semiconductor 2013 requirements for both the high-performance and low-power applications in the 2028 horizon. Thus, ML MoTe2 as channel materials can scale Moore's law down to 3 nm.