Design and analysis of low-power srams
Design and analysis of low-power srams
复制标题
低功耗sram的设计与分析
DOI：
--
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
M. Sharifkhani
中科院分区：
文献类型：
--
作者：
M. Sharifkhani
近年来，电池供电设备的爆炸式增长使得低功耗设计成为优先考虑的事项。此外，嵌入式 SRAM 单元已成为现代 SoC 中的重要模块。 SRAM单元中晶体管数量的不断增加以及缩放技术中MOS晶体管的漏电流激增，使得SRAM单元从动态和静态角度都成为耗电块。由于写操作期间位线电压摆幅较高，因此写功耗在动态功耗中占主导地位。静态功耗主要是由于与分布在阵列中的 SRAM 单元相关的漏电流造成的。此外，随着电源电压降低以解决功耗问题，SRAM单元的数据稳定性近年来已成为主要问题。
为了降低写入功耗，已经提出了多种方案，例如基于行的读出放大单元（SAC）和分层位线读出放大（HBLSA）。然而，这些方案在行上的字数方面对设计施加了架构限制。此外，这些方法的有效性仅限于动态功耗。传统上，已建议降低电池电源电压并利用体效应来减少电池漏电流。然而，电池供电电压的变化会带来较高的动态功耗和降低的电池数据稳定性。通常通过静态噪声容限 (SNM) 进行鉴定，在较低电源电压条件下，单元保留数据的能力会降低。
在本文中，我们从动态角度重新审视数据稳定性的概念。定义了 SRAM 单元数据稳定性的新标准。新标准表明，单元的访问时间和非访问时间（恢复时间）会影响 SRAM 单元中的数据稳定性。速度与稳定性的权衡为低功耗应用大幅降低功耗开辟了新的机会。采用 130nm CMOS 技术实现的测试芯片的实验结果证实了这一概念，并为引入 SRAM 单元的新操作模式奠定了基础。
我们引入了新的架构；分段虚拟接地 (SVGND) 可同时降低 SRAM 单元的动态和静态功耗。得益于 SRAM 单元数据稳定性的新概念，我们向 SRAM 单元引入了访问保留模式（AR-Mode）的新操作模式。在此模式下，被访问的 SRAM 单元可以保留数据，但不会对位线放电。由于位线和单元虚拟地的专有放电，新架构在动态功耗方面优于最近报道的低功耗方案。此外，该架构显着降低了漏电流，因为它在负载和驱动晶体管中都使用了背体偏置。
基于 SVGND 架构的 40Kb SRAM 单元采用 130 nm CMOS 技术实现。正如仿真结果所预期的那样，与传统的和先前报道的低功耗方案相比，实验结果显示出显着的静态和动态功耗降低。
The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. Owing to high bitline voltage swing during write operation, the write power consumption is dominated the dynamic power consumption. The static power consumption is mainly due to the leakage current associated with the SRAM cells distributed in the array. Moreover, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent years.
To reduce the write power consumption, several schemes such as row based sense amplifying cell (SAC) and hierarchical bitline sense amplification (HBLSA) have been proposed. However, these schemes impose architectural limitations on the design in terms of the number of words on a row. Beside, the effectiveness of these methods is limited to the dynamic power consumption. Conventionally, reduction of the cell supply voltage and exploiting the body effect has been suggested to reduce the cell leakage current. However, variation of the supply voltage of the cell associates with a higher dynamic power consumption and reduced cell data stability. Conventionally qualified by Static Noise Margin (SNM), the ability of the cell to retain the data is reduced under a lower supply voltage conditions.
In this thesis, we revisit the concept of data stability from the dynamic perspective. A new criteria for the data stability of the SRAM cell is defined. The new criteria suggests that the access time and non-access time (recovery time) of the cell can influence the data stability in a SRAM cell. The speed vs. stability trade-off opens new opportunities for aggressive power reduction for low-power applications. Experimental results of a test chip implemented in a 130nm CMOS technology confirmed the concept and opened a ground for introduction of a new operational mode for the SRAM cells.
We introduced a new architecture; Segmented Virtual Grounding (SVGND) to reduce the dynamic and static power reduction in SRAM units at the same time. Thanks to the new concept for the data stability in SRAM cells, we introduced the new operational mode of Accessed Retention Mode (AR-Mode) to the SRAM cell. In this mode, the accessed SRAM cell can retain the data, however, it does not discharge the bitline. The new architecture outperforms the recently reported low-power schemes in terms of dynamic power consumption, thanks to the exclusive discharge of the bitline and the cell virtual ground. In addition, the architecture reduces the leakage current significantly since it uses the back body biasing in both load and drive transistors.
A 40Kb SRAM unit based on SVGND architecture is implemented in a 130 nm CMOS technology. Experimental results exhibit a remarkable static and dynamic power reduction compared to the conventional and previously reported low-power schemes as expect from the simulation results.