Four-Element Wide Modulated Bandwidth MIMO Receiver With >35-dB Interference Cancellation
Four-Element Wide Modulated Bandwidth MIMO Receiver With >35-dB Interference Cancellation
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DOI：
10.1109/tmtt.2020.2986441
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发表时间：
2020-04
影响因子：
4.3
通讯作者：
Erfan Ghaderi;A. Ramani;A. Rahimi;D. Heo;S. Shekhar;Subhanshu Gupta
中科院分区：
文献类型：
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作者：
Erfan Ghaderi;A. Ramani;A. Rahimi;D. Heo;S. Shekhar;Subhanshu Gupta
随着小区密度的增加、环境反射的更加复杂以及下一代无线通信的多个网络的共存，主动控制干扰是必要的。现有的空间干扰消除 (SpICa) 无线电接收器架构受到相控天线阵列 (PAA) 产生的空间零点的限制，并且无法覆盖较宽的调制带宽 (BW)。我们提出了一种离散时延补偿技术，用于消除宽调制带宽的空间干扰，以降低数据转换器的动态范围要求。所提出的电路集成了一个基于开关电容器的乘法累加处理器，该处理器结合了可重新配置的相位内插器和时间交织器，用于精确的数字可调延迟以及输入信号与正交矩阵的乘法。数字时间交织器可实现 5 ps 分辨率，可重构范围高达 15 ns。测量结果表明，65 nm CMOS 中的 80 MHz 调制带宽具有超过 35 dB SpICa，功耗为 52 mW。
Active control of interference is necessary with increased cell density, more complicated environmental reflections, and coexistence of multiple networks for next-generation wireless communications. The existing radio receiver architectures for spatial interference cancellation (SpICa) are limited by the spatial nulls created by a phased-antenna array (PAA) and cannot cover wide modulated bandwidths (BWs). We propose a discrete-time-delay-compensating technique for canceling spatial interferences with wide modulated BWs to reduce the dynamic range requirement for the data converter. Integral to the proposed circuit is a switched-capacitor-based multiply-and-accumulate processor that incorporates a reconfigurable phase interpolator and time interleaver for precise digitally tunable delays and multiplication of the input signal to an orthogonal matrix. The digital time interleaver enables 5-ps resolution with a reconfigurable range up to 15 ns. The measured results demonstrate greater than 35-dB SpICa over 80-MHz modulated BWs in the 65-nm CMOS with 52 mW of power consumption.