Evaluation of a soft error tolerance technique based on time and/or space redundancy
Evaluation of a soft error tolerance technique based on time and/or space redundancy
复制标题
基于时间和/或空间冗余的软容错技术的评估
DOI：
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发表时间：
2000
期刊：
影响因子：
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通讯作者：
M. Nicolaidis
中科院分区：
文献类型：
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作者：
L. Anghel;D. Alexandrescu;M. Nicolaidis
IC 技术在通道宽度、电源和速度方面正在接近硅的极限。随着接近这些限制，电路对噪声变得越来越敏感，这将导致不可接受的软错误率。制造测试和定期测试无法应对软错误。因此，即使对于商品应用程序，容错技术也将变得必要。这项工作考虑了基于时间冗余的新软容错技术的实现。使用算术电路作为测试工具来验证该方法。使用围绕事件驱动模拟器实现的内部工具对所提出的容错技术进行了模拟和性能评估。获得的结果表明可以以低成本实现软错误容错。
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. Manufacturing testing and periodic testing cannot cope with soft errors. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation of a new soft error tolerance technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluation of the proposed fault-tolerance technique were made using in-house tools realized around an event driven simulator. The obtained results show that tolerance of soft errors can be achieved at low cost.