3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs
3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs
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DOI：
10.1109/sc.2010.2
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发表时间：
2010-11
期刊：
影响因子：
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通讯作者：
A. Nguyen;N. Satish;J. Chhugani;Changkyu Kim;P. Dubey
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文献类型：
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作者：
A. Nguyen;N. Satish;J. Chhugani;Changkyu Kim;P. Dubey
模具计算在多个时间步骤上扫描空间网格，以执行最近的邻居计算。大量的模板内核的带宽到计算要求很高，它们的性能受到可用的内存带宽的约束。由于内存带宽的增长速度慢于计算，因此模板内核的性能不会随着计算密度的增加而扩展。我们提出了一种新颖的3.5D阻滞算法，该算法对CPU和GPU的芯片记忆执行2.5D空间和时间阻断。所得的算法都可以与线程级和数据级并行性相提并论，并与SIMD宽度和多核接近线性缩放。我们的性能号码更快或与CPU和GPU上的最新模具实现相提并论。我们的7点模具在CPU上的实现是1.5倍，而单个精密浮点输入的GPU比以前报道的数字快1.8倍。对于晶格Boltzmann方法，CPU上的相应加速号为2.1倍。
Stencil computation sweeps over a spatial grid over multiple time steps to perform nearest-neighbor computations. The bandwidth-to-compute requirement for a large class of stencil kernels is very high, and their performance is bound by the available memory bandwidth. Since memory bandwidth grows slower than compute, the performance of stencil kernels will not scale with increasing compute density. We present a novel 3.5D-blocking algorithm that performs 2.5D-spatial and temporal blocking of the input grid into on-chip memory for both CPUs and GPUs. The resultant algorithm is amenable to both thread- level and data-level parallelism, and scales near-linearly with the SIMD width and multiple-cores. Our performance numbers are faster or comparable to state-of-the-art-stencil implementations on CPUs and GPUs. Our implementation of 7-point-stencil is 1.5X-faster on CPUs, and 1.8X faster on GPUs for single- precision floating point inputs than previously reported numbers. For Lattice Boltzmann methods, the corresponding speedup number on CPUs is 2.1X.