Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System
Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System
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DOI：
10.1109/tim.2020.3011490
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发表时间：
2021-01-01
影响因子：
5.6
通讯作者：
Jee, Dong-Woo
中科院分区：
文献类型：
--
作者：
Choi, Kyu-Jin;Jee, Dong-Woo
介绍了一种基于多通道现场可编程门阵列（FPGA）的时间-数字转换器（TDC）及其校准技术。为此，提出了一种基于频率跟踪器的滑动尺度技术和一种移动平均滤波器来提高线性度和分辨率。误差校准技术可以自动检测和校正由于传输延迟的变化和不匹配引起的转换误差。增益校准提取精细TDC的平均桶宽，并解决粗/精插值结构中的任何线性退化。提出的技术应用于在Xilinx Artix-7 FPGA上实现的四通道TDC设计。在350 μ s的宽输入范围内，输出代码的均方根分辨率为2.90-8.03 ps。
A multichannel field-programmable gate array (FPGA)-based time-to-digital converter (TDC) and its calibration techniques are presented. Herein, a frequency-tracker-based sliding- scale technique and a moving-average filter to improve the linearity and resolution are proposed. The error calibration technique automatically detects and corrects conversion errors caused by variations and mismatches in the propagation delays. The gain calibration extracts the average bin width of the fine TDC and resolves any linearity degradation in the coarse/fine interpolation architecture. The proposed techniques were applied to a four-channel TDC design implemented on a Xilinx Artix-7 FPGA. The measured differential and integral nonlinearities of all channels were within 0.51 least significant bit of 4.88 ps. The root-mean-squared resolution of the output code was 2.90-8.03 ps across a wide input range of 350 mu s.