Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection
复制标题
用于锁相环的数字内置自测试以实现故障检测
DOI：
10.1109/ets.2019.8791533
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
S. Ozev
中科院分区：
文献类型：
--
作者：
Mehmet Ince;E. Yilmaz;Wei Fu;Joonsung Park;K. Nagaraj;L. Winemberg;S. Ozev
随着汽车行业获得近乎零缺陷率的压力不断增加，有必要探索针对嵌入式混合信号组件（如锁相环、直流 - 直流转换器和数据转换器）的内置自测试及其他非传统测试技术。本文提出了一种专门针对锁相环故障检测的极低成本内置自测试技术。该方法依靠通过具有噪声特性的伪随机信号在一个位置激励锁相环回路，并通过全数字电路观察回路中另一个位置的响应，从而产生较小的面积和性能开销。内置自测试电路以及被测锁相环是采用65纳米技术设计的。在晶体管和系统级进行的故障模拟表明，大多数导致参数失效的非灾难性故障可以通过所提出的方法检测到。
With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.