Leakage-delay analysis of Ultra-Thin-Body GeOI devices and logic circuits
Leakage-delay analysis of Ultra-Thin-Body GeOI devices and logic circuits
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DOI：
10.1109/vtsa.2011.5872220
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发表时间：
2011-04
期刊：
影响因子：
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通讯作者：
V. Hu;M. Fan;P. Su;C. Chuang
中科院分区：
文献类型：
--
作者：
V. Hu;M. Fan;P. Su;C. Chuang
本文分析了超薄体（UTB） GeOI器件和逻辑电路的泄漏和延迟。研究了温度、通道厚度、栅极长度和输入模式依赖对泄漏/延迟的影响。与亚阈值泄漏主导的SOI器件/电路相比，带对带隧道主导的GeOI器件/电路的泄漏电流对温度、门长和逻辑电路输入模式的敏感性较低。在300°K和同等延迟条件下，较小带隙的GeOI逆变器在Vdd=1V时的漏电流比SOI逆变器大，而在Vdd=0.8V时的漏电流比SOI逆变器小。GeOI双向NAND的泄漏对栅极长度和输入模式的敏感性较低。在400°K时，与SOI逆变器相比，在Vdd=0.6 ~ 1V时，GeOI逆变器显示出更低的泄漏和更低的延迟。采用堆叠的GeOI晶体管不能减少带间隧穿漏；而叠置的GeOI晶体管比叠置的SOI晶体管具有更大的亚阈值泄漏电流降低。
This paper analyzes the leakage and delay of Ultra-Thin-Body (UTB) GeOI devices and logic circuits. The impact of temperature, channel thickness, gate length and input pattern dependence on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI devices/circuits, the band-to-band tunneling dominated leakage current of GeOI devices/circuits show less sensitivity to temperature, gate length and input patterns of logic circuits. At 300°K and comparable delay, GeOI inverter with smaller band-gap shows larger leakage than the SOI inverter at Vdd=1V, while exhibits lower leakage than the SOI inverter at Vdd=0.8V. The leakage of GeOI two-way NAND is less sensitive to gate length and input patterns. At 400°K, GeOI inverter shows both lower leakage and lower delay at Vdd=0.6∼1V compared with the SOI counterpart. The use of stacked GeOI transistors cannot reduce the band-to-band tunneling leakage; while the stacked GeOI transistors show larger subthreshold leakage current reduction compared with the stacked SOI transistors.