Power-aware soft error hardening via selective voltage scaling
Power-aware soft error hardening via selective voltage scaling
复制标题
通过选择性电压缩放实现功率感知软错误强化
DOI：
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复制
发表时间：
2008
期刊：
影响因子：
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通讯作者：
Diana Marculescu
中科院分区：
文献类型：
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作者：
Kai;Diana Marculescu
由于当前的技术缩放趋势，例如缩小特征尺寸和降低电源电压，纳米级集成电路对辐射引起的瞬态故障（软错误）变得越来越敏感。软错误是存储器中的一个重要问题，也是导致逻辑电路可靠性下降的主要因素。本文提出了一种利用双电源电压进行软错误加固的功耗感知方法。在功率开销的约束下，我们提出的框架可以通过选择性电压缩放来最小化电路的软错误率（SER）。平均而言，电路SER可以减少33.45%的各种大小的瞬态毛刺，只有11.74%的能量增加。每降低1%SER，归一化功率延迟面积积的开销为0.64%，是现有最先进方法的1.33倍。
Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking feature sizes and reducing supply voltages. Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage scaling. On average, circuit SER can be reduced by 33.45% for various sizes of transient glitches with only 11.74% energy increase. The overhead in normalized power-delay-area product per 1% SER reduction is 0.64%, 1.33X less than that of existing state-of-the-art approaches.