FPGA Prototyping of Asynchronous Networks-on-Chip
FPGA Prototyping of Asynchronous Networks-on-Chip
复制标题
异步片上网络的 FPGA 原型设计
DOI:
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发表时间:
2008
期刊:
影响因子:
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通讯作者:
Jonas Lassen
中科院分区:
文献类型:
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作者:
Jonas Lassen
Network-on-chip (NoC) is an emerging paradigm for handling the communication in large system-on-chips. This project investigates the ability to prototype
asynchronous NoCs on FPGAs.
The implementation of asynchronous circuits on standard FPGAs is highly experimental, therefore the rst part of the project has been to establish a design
ow for the implementation of asynchronous circuits on FPGAs. In the project
an asynchronous best-effort NoC for an FPGA has been successfully developed.
The NoC implementation consists of a router and network adapters and is implemented using a 4-phase bundled data handshake protocol. Cores connects
to the network using an OCP interface. To demonstrate the NoC it has been
implemented in a small multi-processor prototype using a mesh topology for the
network.