Memory consistency and event ordering in scalable shared-memory multiprocessors
Memory consistency and event ordering in scalable shared-memory multiprocessors
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DOI：
10.1145/325096.325102
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发表时间：
1990
期刊：
影响因子：
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通讯作者：
K. Gharachorloo;D. Lenoski;J. Laudon;Phillip Gibbons;Anoop Gupta;John L. Hennessy
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文献类型：
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作者：
K. Gharachorloo;D. Lenoski;J. Laudon;Phillip Gibbons;Anoop Gupta;John L. Hennessy
可伸缩共享内存多处理器在处理器之间分配内存，并使用可伸缩的互连网络来提供高带宽和低延迟的通信。此外，存储器访问被高速缓存、缓冲和流水线化，以桥接慢速共享存储器和快速处理器之间的差距。除非仔细控制，否则这种架构优化可能导致内存访问的执行顺序与程序员预期的顺序不同。允许的存储器访问顺序的集合形成了体系结构的存储器一致性模型或事件顺序模型.本文介绍了一种新的存储器一致性模型，称为释放一致性，它允许比以前提出的模型更多的缓冲和流水线。开发了一个用于对共享访问进行分类和对事件排序进行推理的框架。释放一致性模型是等价的顺序一致性模型的并行程序具有足够的同步。可能的性能增益从发布一致性模型的不太严格的约束进行了探讨。最后，实际的实施问题进行了讨论，集中在可扩展的架构相关的问题。
Scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory and the fast processors. Unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.This paper introduces a new model of memory consistency, calledrelease consistency, that allows for more buffering and pipelining than previously proposed models. A framework for classifying shared accesses and reasoning about event ordering is developed. The release consistency model is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. Possible performance gains from the less strict constraints of the release consistency model are explored. Finally, practical implementation issues are discussed, concentrating on issues relevant to scalable architectures.