Implementation on FPGA of a LUT-Based atan(Y/X) Operator Suitable for Synchronization Algorithms
Implementation on FPGA of a LUT-Based atan(Y/X) Operator Suitable for Synchronization Algorithms
复制标题
适合同步算法的基于LUT的atan(Y/X)算子的FPGA实现
DOI：
10.1109/fpl.2007.4380692
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
J. Valls
中科院分区：
文献类型：
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作者：
R. Gutierrez;J. Valls
本文提出了一种适用于吞吐量为20 MHz的宽带通信应用的ATAN(Y/X)运算的计算结构。该结构基于LUT方法，相对于基于CORDIC算法的ATAN(Y/X)算子具有更低的功耗和更低的延迟。该结构可以在两个时钟周期内计算ATAN(Y/X)，其功耗比相同延迟的CORDIC低49%。
This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture is based on LUT methods and achieves lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm with a lower latency. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC with the same latency.