Interconnect Challenges in a Many Core Compute Environment
Interconnect Challenges in a Many Core Compute Environment
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多核计算环境中的互连挑战
DOI：
10.1109/hoti.2009.37
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
J. Bautista
中科院分区：
文献类型：
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作者：
J. Bautista
已经确定的是，未来，在过去二十年中提供的大约2倍/2年的性能改进将主要来自并行性，而不是由于相关的功耗挑战而增加时钟频率。如果软件和工具继续随着内核和线程数而良好地扩展，那么大的内核数在存储器层次结构和管芯上、封装内和封装外的互连带宽方面都带来了严重的挑战。对预期未来工作负载的模拟有助于隔离可能发生特定瓶颈的地方。在芯片堆叠和封装互连方面都需要新技术。这些解决方案将在物理层带来巨大的变化，这可能会破坏向后兼容性。此外，这些潜在的方法是特定于细分市场的，并且涉及性能、成本和功率的复杂权衡。本演示文稿将探讨几种方法，重点介绍潜在的解决方案和未来可能的应用程序驱动的带宽要求。
It is already established that going forward, the roughly 2x/2yr performance improvements delivered over the last two decades will primarily come through parallelism rather than increasing clock frequencies due to associated power challenges. Provided software and tools continue to scale well with core and thread count, large core counts bring serious challenges both in the memory hierarchy and interconnect bandwidth both on-die, within the package, and off package. Simulations on anticipated future workloads help isolate where specific bottlenecks are likely to occur. New technologies both in die stacking and package- to-package interconnects will be required. These solutions will bring dramatic changes in the physical layer that may well break backward compatibility. Furthermore, these potential approaches are segment specific and involve complex tradeoffs of performance, cost, and power. This presentation will explore several approaches highlighting potential solutions and bandwidth requirements driven by likely future applications.