Simulation of Fractal Immittance by Ladder Circuits
Simulation of Fractal Immittance by Ladder Circuits
复制标题
分形导抗的梯形电路仿真
DOI：
10.1080/10587250108024711
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
K. Saito
中科院分区：
文献类型：
--
作者：
M. Sugi;Y. Hirano;Y. Miura;K. Saito
摘要 分形导纳FD以导纳wα表示，a的取值范围为0<a<1，从基于分布弛豫时间（DRT）模型的优化电路开始，通过有限数量电阻和电容的梯形电路进行仿真。由此设计的 a = 1/2 的 DRT 等效梯形图，例如，被发现比由相同梯级组成的传统梯形图更有效：对于 5 个十进制的带宽，相位角误差为 ±2°，例如，传统梯形图涉及 6.426 × 103 个相同的梯级，而 11 个梯级对于 DRT 等效电路来说就足够了。
Abstract Fractal immittance FD, expressed by an admittance w α with an optional value of a within the range 0 <a<1, is simulated by ladder circuits with finite numbers of resistors and capacitors starting from the optimized circuit based on the distributed-relaxation-time (DRT) model. Thus designed DRT-equivalent ladder with a = 1/2, e.g., is found to be far more effective than the conventional ladder composed of identical rungs: for the bandwidth of 5 decades with a phase-angle error of ±2°, e.g., the conventional ladder involves 6.426 × 103 identical rungs, while 11 rungs are sufficient for the DRT-equivalent circuit.