A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology
A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology
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采用28nm SOI技术的高速动态可重构处理器的设计与实现
DOI：
10.1109/fpl.2014.6927438
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
H. Amano
中科院分区：
文献类型：
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作者：
Toru Katagiri;H. Amano
尽管动态可重构处理器阵列 (DRPA) 由于其高能效而对嵌入式设备有利，但许多最新的移动设备需要执行越来越以性能为中心的作业。提高时钟频率的一种相当紧张的方法是在每个 PE 中引入流水线结构。然而，由于多个 PE 之间的数据危险，这会导致管道频繁停顿。为了减轻PE之间数据危险的影响，我们提出了一种微小的向量指令机制。使用单个向量指令，可以在PE的流水线中连续处理少量数据。在不增加硬件上下文数量以及配置数据量的情况下消除管道停顿。基于采用28nm SOI工艺技术实现的评估结果，具有微小矢量指令的DRPA（DRPA-TVI）与基础DRPA相比，性能提高了2.4三倍，而面积和功耗仅略有增加。
Although dynamically reconfigurable processor arrays (DRPAs) are advantageous for embedded devices because of their high energy efficiency, many of the recent mobile devices are required to execute increasingly performance-centric jobs. One fairly straingtfoward way of increasing the clock frequency is introducing a pipelined structure into each PE. However, this results in frequent pipeline stalls due to the data hazard between multiple PEs. In order to mitigate the effect of data hazard between PEs, we propose a tiny vector instruction mechanism. With a single vector instruction, a small amount of data is continuously processed in the pipeline of the PE. Pipeline stalls are removed without increasing the number of hardware contexts, and thus the amount of configuration data. Evaluation results based on the implementation using 28nm SOI process technology, a DRPA with tiny vector instructions (DRPA-TVI) improves the performance by 2.4 three times compared to a base DRPA with just a small increase of area and power consumption.