Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration
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通过电荷水平感知先行部分恢复减少 DRAM 延迟
DOI：
10.1109/micro.2018.00032
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
O. Mutlu
中科院分区：
文献类型：
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作者：
Yaohua Wang;Arash Tavakkol;Lois Orosa;Saugata Ghose;Nika Mansouri;Minesh Patel;Jeremie S. Kim;Hasan Hassan;Mohammad Sadrosadati;O. Mutlu
较长的 DRAM 访问延迟是系统性能的主要瓶颈。为了访问 DRAM 中的数据，存储器控制器 (1) 激活（即打开）单元阵列中的一行 DRAM 单元，(2) 将激活的单元中的电荷恢复到其满电平，(3) 对激活的行执行读写操作，以及 (4) 预充电单元阵列以准备下一次激活。恢复操作占总 DRAM 访问延迟的很大一部分（高达 43.6%）。我们发现两种常见情况，其中 DRAM 执行的恢复操作不需要完全恢复激活的 DRAM 单元的电荷水平，我们可以利用它来减少恢复延迟。首先，DRAM 行会定期刷新（即恢复到满充电状态），以避免由于单元的电荷泄漏而导致数据丢失。即将刷新的 DRAM 行的电荷水平只需部分恢复，提供刚好足够的电荷，以便刷新可以正确检测单元的数据值。其次，即将再次激活的 DRAM 行的电荷水平只能部分恢复，为激活提供刚好足够的电荷以正确检测数据值。然而，部分恢复需要谨慎进行：对于即将再次激活的行，仅恢复到可能的最低电荷水平可能会破坏减少高电荷行激活时间的补充机制的优势。为了有效减少激活和恢复的延迟，我们提出了电荷水平感知的先行部分恢复（CAL）。 CAL 由两个关键部分组成。首先，CAL准确预测下一次访问时间，即当前恢复操作与下一次激活同一行之间的时间。其次，CAL使用预测的下一次访问时间和下一次刷新时间来减少恢复时间，确保部分电荷恢复的量足以维持减少高充电行激活时间的好处。我们在内存控制器中完全实现了 CAL，无需对 DRAM 模块进行任何更改。在各种应用中，我们发现 CAL 将 8 核系统的平均性能提高了 14.7%，并将平均 DRAM 能耗降低了 11.3%。
Long DRAM access latency is a major bottleneck for system performance. In order to access data in DRAM, a memory controller (1) activates (i.e., opens) a row of DRAM cells in a cell array, (2) restores the charge in the activated cells back to their full level, (3) performs read and write operations to the activated row, and (4) precharges the cell array to prepare for the next activation. The restoration operation is responsible for a large portion (up to 43.6%) of the total DRAM access latency. We find two frequent cases where the restoration operations performed by DRAM do not need to fully restore the charge level of the activated DRAM cells, which we can exploit to reduce the restoration latency. First, DRAM rows are periodically refreshed (i.e., brought back to full charge) to avoid data loss due to charge leakage from the cell. The charge level of a DRAM row that will be refreshed soon needs to be only partially restored, providing just enough charge so that the refresh can correctly detect the cells' data values. Second, the charge level of a DRAM row that will be activated again soon can be only partially restored, providing just enough charge for the activation to correctly detect the data value. However, partial restoration needs to be done carefully: for a row that will be activated again soon, restoring to only the minimum possible charge level can undermine the benefits of complementary mechanisms that reduce the activation time of highly-charged rows. To enable effective latency reduction for both activation and restoration, we propose charge-level-aware look-ahead partial restoration (CAL). CAL consists of two key components. First, CAL accurately predicts the next access time, which is the time between the current restoration operation and the next activation of the same row. Second, CAL uses the predicted next access time and the next refresh time to reduce the restoration time, ensuring that the amount of partial charge restoration is enough to maintain the benefits of reducing the activation time of a highly-charged row. We implement CAL fully in the memory controller, without any changes to the DRAM module. Across a wide variety of applications, we find that CAL improves the average performance of an 8-core system by 14.7%, and reduces average DRAM energy consumption by 11.3%.