Energy efficient parameterized FFT architecture
Energy efficient parameterized FFT architecture
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节能参数化 FFT 架构
DOI：
10.1109/fpl.2013.6645545
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
V. Prasanna
中科院分区：
文献类型：
--
作者：
Ren Chen;H. Le;V. Prasanna
在本文中，我们为FPGAS上的能源有效设计重新审视了参数化的FFT架构，以确定我们首先通过改变算法映射来实现设计空间的设计权衡。参数，例如垂直和水平并行性的程度，这些参数是基于分解的FFT算法的。通过经验选择所选体系结构参数的值，包括内存元素的类型，互连网络的类型和管道阶段的数量。 ：能源效率（定义为每焦点的操作数）和能量×面积×时间（EAT）复合度量。各种性能指标的参数。设计。
In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. A parameterized FFT architecture is proposed to identify the design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize decomposition based FFT algorithms. Then we explore an energy efficient design by empirical selection on the values of the chosen architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The trade offs between energy, area, and time are analyzed using two performance metrics: the energy efficiency (defined as the number of operations per Joule) and the Energy×Area×Time (EAT) composite metric. From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N-point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.