An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory
An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory
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DOI：
10.1109/tbcas.2013.2255873
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发表时间：
2014-02-01
影响因子：
5.1
通讯作者：
Indiveri, Giacomo
中科院分区：
文献类型：
--
作者：
Moradi, Saber;Indiveri, Giacomo
我们提出了一种混合模拟/数字超大规模集成（VLSI）实现的尖峰神经网络与可编程突触权重。突触权重值存储在异步静态随机存取存储器（SRAM）模块中，该SRAM模块与快速电流模式事件驱动DAC接口，用于产生具有适当幅度值的突触电流。这些电流进一步集成的电流模式积分器突触，以产生生物药理学现实的时间动态。突触输出电流，然后集成的紧凑和高效的集成和发射硅神经元电路与尖峰频率适应和可调的不应期和尖峰复位电压设置。所制造的芯片包括总共32 x 32个SRAM单元、4 x 32个突触电路和32 x 1个硅神经元。它充当收发器，接收输入中的异步事件，在输入尖峰上使用混合模拟/数字电路执行神经计算，并最终在输出中产生数字异步事件。输入、输出和突触权重值使用基于地址事件表示（AER）的公共通信协议被传送到芯片/从芯片传送。使用这种表示，可以将设备连接到工作站或微控制器，并探索不同类型的尖峰定时相关可塑性（STDP）学习算法的效果，以更新SRAM模块中的突触权重值。我们目前的实验结果证明芯片上存在的所有电路的正确操作。
We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 x 32 SRAM cells, 4 x 32 synapse circuits and 32 x 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip.