Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments
Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments
复制标题
用于高能物理实验的单片 HV-CMOS 像素探测器新颖原型的表征
DOI：
10.1088/1748-0221/12/06/c06009
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发表时间：
2017
影响因子：
1.3
通讯作者：
E. Vilella
中科院分区：
文献类型：
--
作者：
S. Terzo;E. Cavallaro;R. Casanova;F. D. Bello;F. Förster;S. Grinstein;I. Perić;C. Puigdengoles;B. Ristic;M. V. B. Pinto;E. Vilella
计划于2024年对大型强子对撞机高光度阶段的ATLAS实验进行升级，预计将用完全由硅器件制成的新的内跟踪器(ITK)取代现有的内探测器(ID)。采用高压CMOS(HV-CMOS)技术构建的耗尽有源像素传感器被研究为覆盖像素探测器最外层的大片区域的一种选择，并且对于单片器件的开发特别感兴趣，这将降低相对于目前的混合组件的生产成本和材料预算。为此，H35DEMO是一款大面积HV-CMOS演示芯片，由KIT、IFAE和利物浦大学共同设计，采用AMS 350 nm CMOS工艺生产。它由四个像素矩阵和附加测试结构组成。其中两个矩阵包括放大器和鉴别级，因此被设计为作为单片探测器操作。在这些器件中，信号主要是通过施加100V数量级的偏置电压获得的小耗尽体积中的电荷漂移来产生的。此外，为了提高芯片的抗辐射能力，该技术允许将电子设备封装在同样用作收集电极的深N-Well中。在这篇文章中，将介绍H35DEMO芯片的特性和在CERN SPS上首次对具有高能介子的单片CMOS阵进行束流测试的结果。
An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purpose the H35DEMO, a large area HV-CMOS demonstrator chip, was designed by KIT, IFAE and University of Liverpool, and produced in AMS 350 nm CMOS technology. It consists of four pixel matrices and additional test structures. Two of the matrices include amplifiers and discriminator stages and are thus designed to be operated as monolithic detectors. In these devices the signal is mainly produced by charge drift in a small depleted volume obtained by applying a bias voltage of the order of 100V. Moreover, to enhance the radiation hardness of the chip, this technology allows to enclose the electronics in the same deep N-WELLs which are also used as collecting electrodes. In this contribution the characterisation of H35DEMO chips and results of the very first beam test measurements of the monolithic CMOS matrices with high energetic pions at CERN SPS will be presented.