22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme
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22.1 采用数据总线窗口扩展技术和协同片上 ECC 方案的 1.1V 16GB 640GB/s HBM2E DRAM
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发表时间：
2020
期刊：
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通讯作者：
Jung
中科院分区：
文献类型：
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作者：
C. Oh;K. Chun;Y. Byun;Yong;So;Yesin Ryu;Jaewon Park;Si;S. Cha;Dong;Jungyu Lee;J. Son;Byung;Seong;Beomyong Kil;Sungoh Ahn;B. Lim;Yong;Ki;Myung;S. Baek;J.Y. Noh;Jaewook Lee;Seungseob Lee;Sooyoung Kim;Bo;Seouk;Jin;Hye;Hyuk;J. Kong;Kyomin Sohn;N. Kim;Kwang;Jung
快速发展的人工智能（AI）技术，如深度学习，已成功部署在各种应用中：如图像识别，医疗保健和自动驾驶。AI技术的这种快速发展和成功部署是可能的，因为加速器的出现，例如GPU和TPU，具有更高的数据吞吐量。这反过来又需要具有大容量和高带宽的增强型存储器系统[1]; HBM由于其高速和低功耗特性而成为最受欢迎的高带宽存储器技术，2.5D硅中介层技术促进了1024 IO，以及通过硅通孔（TSV）堆栈技术实现的大容量[2]。上一代HBM2支持8 GB容量，具有8个DRAM管芯的堆栈（即，8-高堆栈）和341 GB/s（2.7Gb/s/引脚）带宽[3]。HBM行业的趋势是每年15 - 20%的速度提高，而产能每两年增加1.5- 2倍。本文提出了一种16 GB的HBM2 E，通过电路和设计技术将其带宽提高到640 GB/s（5Gb/s/pin），同时在第二代10 nm DRAM工艺中提供稳定的位单元操作：其特征在于（1）数据总线窗口扩展技术以科普减小的$T_{CCO}$，（2）被设计用于高速稳定操作的功率输送网络（PDN），（3）用于可靠地提供大容量的协同管芯上ECC方案，以及（4）用于高速有效地测试大容量存储器的MBIST解决方案。
Rapidly evolving artificial intelligence (Al) technology, such as deep learning, has been successfully deployed in various applications: such as image recognition, health care, and autonomous driving. Such rapid evolution and successful deployment of Al technology have been possible owing to the emergence of accelerators, such as GPUs and TPUs, that have a higher data throughput. This, in turn, requires an enhanced memory system with large capacity and high bandwidth [1]; HBM has been the most preferred high-bandwidth memory technology due to its high-speed and low-power characteristics, and 1024 IOs facilitated by 2.5D silicon interposer technology, as well as large capacity realized by through-silicon via (TSV) stack technology [2]. Previous-generation HBM2 supports 8GB capacity with a stack of 8 DRAM dies (i.e., 8-high stack) and 341GB/s (2.7Gb/s/pin) bandwidth [3]. The HBM industry trend has been a speed improvement of 15~20% every year, while capacity increases by 1.5-2x every two years. In this paper, we present a 16GB HBM2E with circuit and design techniques to increase its bandwidth up to 640GB/s (5Gb/s/pin), while providing stable bit-cell operation in the 2nd generation of a 10nm DRAM process: featuring (1) a data-bus window-extension technique to cope with reduced $t_{cco}$, (2) a power delivery network (PDN) designed for stable operation at a high speed, (3) a synergetic on-die ECC scheme to reliably provide large capacity, and (4) an MBIST solution to efficiently test large capacity memory at a high speed.