EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance
EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance
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DOI：
10.1109/isvlsi51109.2021.00067
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发表时间：
2021-07
期刊：
影响因子：
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通讯作者：
Krithika Dhananjay;E. Salman
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文献类型：
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作者：
Krithika Dhananjay;E. Salman
绝热电路具有实现超低功耗的潜力，同时还表现出对电源侧通道攻击的固有抵抗能力。在这项工作中，提出了一种新的绝热逻辑族，并将其应用于能效和硬件安全都是首要考虑的轻量级设备。通过量化归一化能量差(NED)和归一化标准差(NSD)来评估所提出的绝热逻辑的旁路安全特性。将这些度量与现有的安全绝热逻辑族进行了比较。使用65 nm技术节点在13.56 MHz的RFID频率下执行模拟。在所提出的逻辑系列中，NAND/AND和NOR/OR门每次转换的平均功耗最高可降低34.5%，而NED增加3%，NSD增加1.5%。建议的方法还减少了40%的晶体管数量。此外，所提出的绝热逻辑系列不需要任何外部四相输入信号来实现与输入无关的功耗，从而显著降低了总体开销。
Adiabatic circuits have the potential to achieve ultra-low power consumption while also exhibiting inherent resistance against power side-channel attacks. A novel adiabatic logic family is proposed in this work with application to lightweight devices where both energy efficiency and hardware security are of primary concern. The side-channel security characteristics of the proposed adiabatic logic are evaluated by quantifying normalized energy deviation (NED) and the normalized standard deviation (NSD). These metrics are compared with the existing secure adiabatic logic families. The simulations are performed at an RFID frequency of 13.56 MHz using a 65 nm technology node. The average energy per transition consumed by the NAND/AND and NOR/OR gates in the proposed logic family is up to 34.5% lower at the expense of 3% increase in the NED and 1.5% increase in the NSD. The proposed approach also reduces the number of transistors by 40%. Furthermore, the proposed adiabatic logic family does not require any external four-phase input signals to achieve input-independent power consumption, thereby significantly reducing the overall overhead.