Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects
复制标题
存在制造缺陷时存在电迁移引起的退化的 IC 互连的寿命预测和可靠性设计
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
A. Chatterjee
中科院分区：
文献类型：
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作者：
Xiangdong Xuan;A. Singh;A. Chatterjee
由于电迁移（EM）导致的IC互连的退化受到互连迹线上的物理缺陷和瑕疵的强烈影响，这些物理缺陷和瑕疵通过增加的电流密度和升高的温度显著加速EM损坏。在这项工作中，集成电路可靠性模拟器的开发，将这些物理缺陷对电路互连可靠性的影响。基于一种统计缺陷建模方法，评估了电磁退化条件下含缺陷互连的电路级可靠性。这也被成功地纳入了一个名为ARET的工具。此外，还开发了用于识别电路可靠性热点的方法。在此基础上，提出了局部可靠性设计（LDFR）的概念，以提高电迁移下的电路级可靠性。
The degradation of IC interconnects due to electromigration (EM) is strongly influenced by physical defects and imperfections on interconnect traces that significantly accelerate EM damage through increased current density and elevated temperature. In this work, an IC reliability simulator is developed to incorporate the effect of these physical defects on circuit interconnect reliability. Based on a statistical defect modeling approach, circuit-level reliability with defective interconnects under EM degradation is evaluated. This has also been successfully integrated into a tool called ARET. Additionally, an approach for identifying circuit reliability hotspots has also been developed. Based on this hotspot identification, the concept of local design-for-reliability (LDFR) is proposed for improved circuit-level reliability under electromigration.