Opportunities and challenges for Ge CMOS - Control of interfacing field on Ge is a key
Opportunities and challenges for Ge CMOS - Control of interfacing field on Ge is a key
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DOI：
10.1016/j.mee.2009.03.052
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发表时间：
2009-07-01
影响因子：
2.3
通讯作者：
Nagashio, Kosuke
中科院分区：
文献类型：
--
作者：
Toriumi, Akira;Tabata, Toshiyuki;Nagashio, Kosuke
Ge CMOS 对于后尺寸缩放的 Si-CMOS 非常有吸引力。然而，我们必须解决材料及其界面控制方面的许多挑战。在本文中，我们讨论栅极堆叠形成和源极/漏极工程，以及它们对 n- 和 p-MOSFET 性能的影响。由于在相对较低的温度（大约 500 摄氏度）下发生的 GeO 解吸会显着降低 Ge 界面的性能，因此很难通过简单的热预算控制来控制 Ge 栅极堆叠的形成。此外，Ge/金属界面处的强费米能级钉扎是源极/漏极工程中的一个大问题。在讨论了控制 p-FET 和 n-FET 界面处的解吸和费米能级钉扎的方法之后，我们讨论了电子和空穴迁移率的当前状态。 (C) 2009 Elsevier B.V. 保留所有权利。
Ge CMOS is very attractive for the post size-scaled Si-CMOS. However, we have to tackle a number of challenges with regard to materials and their interface control. In this paper, we discuss gate stack formation and source/drain engineering, as well as their implications for the performance of n- and p-MOSFETs. Because the Ge interface is significantly degraded by the GeO desorption occurring at a relatively low temperature (similar to 500 degrees C), it is very hard to control Ge gate stack formation by a simple thermal budget control. In addition, strong Fermi-level pinning at the Ge/metal interface is a big problem in source/drain engineering. After discussing ways to control this desorption and Fermi-level pinning at the interface in both p-FETs and n-FETs, we discuss our current status of both electron and hole mobilities. (C) 2009 Elsevier B.V. All rights reserved.