An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles
An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles
复制标题
基于保守并行离散事件原理的高效TLM/T建模与仿真环境
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
A. Greiner
中科院分区：
文献类型：
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作者：
E. Viaud;F. Pêcheux;A. Greiner
本文提出了一种创新的仿真方案，以加快仿真的多集群多处理器系统芯片在TLM/T（transaction level model with time）的抽象级别。SoC架构的硬件组件是用标准SystemC编写的。目标是描述在给定硬件架构上运行的给定软件应用的动态行为（包括互连中的动态争用和该高速缓存效应），以便为系统设计者提供与周期精确仿真相同的可靠定时信息，其仿真速度类似于TLM仿真。其核心思想是将并行离散事件仿真（PDES）技术应用于一组通信SystemC SC-线程。实验结果表明，与BCA仿真（总线周期精确）相比，仿真加速高达50倍，时序误差低于10-3
The paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (transaction level model with time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply parallel discrete event simulation (PDES) techniques to a collection of communicating SystemC SC-THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (bus cycle accurate), for a timing error lower than 10-3