Tag tables
Tag tables
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标签表
DOI：
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发表时间：
2015
期刊：
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通讯作者：
Mikko H. Lipasti
中科院分区：
文献类型：
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作者：
Sean Franey;Mikko H. Lipasti
标签表能够为超大集关联高速缓存（如 3D DRAM 集成所提供的高速缓存）存储标签，具有细粒度的块大小（如 64B），开销低，可在处理器芯片的 SRAM 中实现。这种方法有别于以往采用小块尺寸的方案，后者认为 DRAM 高速缓存的片上标签阵列过于昂贵，因此将标签阵列与数据一起存储在 DRAM 中。标签表利用应用程序的自然空间位置性，通过紧凑的 "基数加偏移 "编码跟踪高速缓存中的数据位置，从而避免了传统标签阵列的高昂开销。此外，标签表还利用了前向页表结构的按需性质，只为那些与缓存中当前存在的数据相对应的条目分配存储空间，而不是传统标签阵列所带来的静态成本。通过高关联性，我们发现标签表的平均性能比以前最先进的合金缓存提高了 10%以上，由于片上查找速度快，比 Loh-Hill 缓存提高了 44%，在一系列具有高 L3 错失率的多线程和多编程工作负载中，比无 L4 系统提高了 58%。
Tag Tables enable storage of tags for very large set-associative caches - such as those afforded by 3D DRAM integration - with fine-grained block sizes (e.g. 64B) with low enough overhead to be feasibly implemented on the processor die in SRAM. This approach differs from previous proposals utilizing small block sizes which have assumed that on-chip tag arrays for DRAM caches are too expensive and have consequently stored them with the data in the DRAM itself. Tag Tables are able to avoid the costly overhead of traditional tag arrays by exploiting the natural spatial locality of applications to track the location of data in the cache via a compact "base-plus-offset" encoding. Further, Tag Tables leverage the on-demand nature of a forward page table structure to only allocate storage for those entries that correspond to data currently present in the cache, as opposed to the static cost imposed by a traditional tag array. Through high associativity, we show that Tag Tables provide an average performance improvement of more than 10% over the prior state-of-the-art - Alloy Cache - 44% more than the Loh-Hill Cache due to fast on-chip lookups, and 58% over a no-L4 system through a range of multithreaded and multiprogrammed workloads with high L3 miss rates.