Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory
Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory
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DOI：
10.1109/ted.2017.2756071
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发表时间：
2017-11-01
影响因子：
3.1
通讯作者：
Wong, H. -S. Philip
中科院分区：
文献类型：
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作者：
Fong, Scott W.;Neumann, Christopher M.;Wong, H. -S. Philip
高复位能量是相变存储器（PCM）装置的持续问题。先前的工作表明，较小的PCM开关体积和热隔离可以降低复位能量。在本文中，我们制作和测量了一个平面限制PCM器件与多层双层堆叠（DLS）的SiO2/Al 2 O3绝缘体。接触面积为500 × 20 nm、长度为2 μ m的器件显示出极低的复位能量（18.25 +/- 15.8 pJ）和低的复位电流密度（0.94 +/- 0.51 MA/cm（2））。与SiO2隔离器件相比，实施DLS可使复位能量降低60%。
High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 x 20 nm and lengths of 2 mu m show exceptionally low reset energies of 18.25 +/- 15.8 pJ and low reset current densities of 0.94 +/- 0.51 MA/cm(2). Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.