A Comparitive Study of On-Chip Clock Generators Using a-IGZO TFTs for Flexible Electronic Systems

A Comparitive Study of On-Chip Clock Generators Using a-IGZO TFTs for Flexible Electronic Systems
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DOI:
10.1109/ifetc.2018.8583926
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发表时间:
2018-08
期刊:
2018 International Flexible Electronics Technology Conference (IFETC)
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通讯作者:
Nishtha Wadhwa;J. Martins;P. Bahubalindruni;Sujay Deb;P. Barquinha
Nishtha Wadhwa;J. Martins;P. Bahubalindruni;Sujay Deb;P. Barquinha
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其他
文献类型:
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作者:
Nishtha Wadhwa;J. Martins;P. Bahubalindruni;Sujay Deb;P. Barquinha

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本文对采用非晶铟镓锌氧化物(a- igzo)薄膜晶体管(TFTs)实现柔性电子系统片上时钟发生器的环形振荡器(RO)进行了比较研究。采用IGZO TFTs实现了不同逆变器拓扑的五级RO,包括二极管连接负载、电容式自举(BS)、伪cmos和伪cmos自举架构。这些拓扑已经在类似条件下使用不同电源(10v, 15v和20v)在节奏环境中使用内部IGZO TFT模型进行了模拟。在所有架构中,电容式自启动RO确保了MHz数量级的最高工作频率和VDD的82%的输出摆幅。而基于伪cmos的RO功耗最低,为μW量级,输出摆幅为VDD的57%。另一方面,伪CMOS和自举的结合保证了VDD 95%的最高电压摆幅。在功率延迟积(PDP)方面,bsro相对于其他拓扑结构具有优势。这项工作为设计人员为给定应用选择特定拓扑提供了清晰的见解,主要用于基于要求的柔性电子系统的片上时钟生成。
This paper presents a comparitive study of ring oscillators (RO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs) to implement on-chip clock generator for flexible electronic systems. A five-stage RO has been implemented with different inverter topologies using IGZO TFTs, which includes Diode connected load, Capacitive bootstrapping (BS), Pseudo-CMOS and Pseudo-CMOS bootstrapping architectures. These topologies have been simulated using in-house IGZO TFT models under similar conditions using different power supplies (10 V, 15 V and 20 V) in cadence environment. Among all architechtures Capacitive bootstrapping RO has ensured highest frequency of operation in the order of MHz and an output swing of 82% of VDD. Whereas, Pseudo-CMOS based RO provides the lowest power consumption in the order of μW with an output swing of 57% of VDD. On the other hand, the combination of Pseudo CMOS and bootstrapping has ensured highest voltage swing of 95% of VDD. In terms of power delay product (PDP) BS RO is superior with respect to other topologies. This work provides a clear insight to the designer to choose a particular topology for given application, mainly for on-chip clock generation for flexible electronic systems based on the requirements.