FPGA Implementation Technique for Power Consumption Aware Tamper Resistance Accelerator of Lightweight PUF

FPGA Implementation Technique for Power Consumption Aware Tamper Resistance Accelerator of Lightweight PUF
复制标题

轻量级PUF功耗感知防篡改加速器的FPGA实现技术

DOI:
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发表时间:
2017
期刊:
影响因子:
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通讯作者:
and M. Yoshikawa
and M. Yoshikawa
中科院分区:
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文献类型:
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作者:
Y. Ikezaki;Y. Nozaki;H. Nagata;and M. Yoshikawa

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