A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process
A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process
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采用 90nm CMOS 工艺的 4-6 位 3GS/s 闪存 ADC 的低反冲比较器
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
A. Alvandpour
中科院分区：
文献类型：
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作者：
Timmy Sundström;A. Alvandpour
本文提出了一种基于感测放大器型比较器的减回比较器。反冲电荷和由此产生的电压峰值降低了6倍，这对应于输入驱动器和电阻阶梯的功率降低相同幅度。采用该比较器的4-6位3-GS/s低功耗闪存ADC已在90nm CMOS工艺中实现。对输入驱动器和电阻梯的要求显著降低，使ADC的整体功耗降低了50%。
This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.