Experimental and simulation studies of single-electron-transistor-based multiple-valued logic
Experimental and simulation studies of single-electron-transistor-based multiple-valued logic
复制标题
基于单电子晶体管的多值逻辑的实验与仿真研究
DOI：
10.1109/ismvl.2003.1201415
复制
发表时间：
2003
期刊：
影响因子：
--
通讯作者：
Yasuo Takahashi
中科院分区：
文献类型：
--
作者：
H. Inokawa;Yasuo Takahashi
利用单电子晶体管（SET）的周期性漏极电流-栅极电压特性构造多值逻辑（MVL）的基本元件，如通用文字门和量化器。为了弥补SET的小增益和小的适用电压，混合SET-MOSFET的方案，提出和实验证明，采用CMOS兼容的图案相关氧化（PADOX）技术。我们还成功地再现了使用SPICE电路模拟器与一个紧凑的分析SET模型的结果，并估计所提出的MVL的性能。
Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.