HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires
HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires
复制标题
HILL：针对多租户 FPGA 长线信息泄露的硬件隔离框架
DOI：
10.1109/icfpt47387.2019.00060
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发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Xiaolin Xu
中科院分区：
文献类型：
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作者：
Yukui Luo;Xiaolin Xu
FPGA最近已部署在多租户云中，以提供高性能的计算功能。 FPGA的这种部署为对手创造了新的攻击表面。最近已经证明，FPGA长系之间的电容串扰可以用作侧通道来提取秘密信息。在本文中，我们介绍了Hill：一个硬件隔离框架，以防止在多租户FPGA长系上泄漏信息。作为防御框架，Hill可以优先考虑关键安全硬件实例的放置和路由，并将其与其他部件和租户隔离。对于使用FPGA长系（例如UART，PCIE和AXI4）的数据和通信界面，Hill采用了一种长线混淆技术来减少侧通道泄漏。我们使用两种普遍的FPGA开发工具：Xilinx ISE 14.7和Vivado 2018.3评估Xilinx Artix-7 FPGA的山丘性能。实验结果表明，山丘可以有效地将串扰引起的侧渠道泄漏减少138次。长线混淆技术将侧向通道泄漏和秘密钥匙之间的相关性从81.7％降低到50.3％，这几乎是随机猜测。
FPGA has recently been deployed in the multi-tenant cloud to provide high-performance computing capabilities. Such deployment of FPGA creates a new attack surface for adversary. It has been recently demonstrated that the capacitive crosstalk between FPGA long-wires can be used as a side-channel to extract secret information. In this paper, we present HILL: a Hardware Isolation framework against information Leakage on multi-tenant FPGA Long-wires. As a defense framework, HILL can prioritize the placement and routing of security-critical hardware instances and isolate them from other parts and tenants. For data and communication interfaces that use FPGA long-wires, such as UART, PCIe, and AXI4, HILL employs a long-wire obfuscation technique to reduce the side-channel leakage. We evaluate the performance of HILL with Xilinx Artix-7 FPGAs using two prevalent FPGA development tools: Xilinx ISE 14.7 and Vivado 2018.3. The experimental results demonstrate that HILL can effectively reduce the crosstalk-caused side-channel leakage by 138 times. The long-wire obfuscation technique reduces the correlation between the side-channel leakage and secret key from 81.7% to 50.3%, which is close to random guess.