D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM / MRAM hybrid memory
D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM / MRAM hybrid memory
复制标题
D-MRAM 缓存：利用 3T-1MTJ DRAM / MRAM 混合内存提高能源效率
DOI：
10.7873/date.2013.363
复制
发表时间：
2013
期刊：
影响因子：
--
通讯作者：
Hiroshi Nakamura
中科院分区：
文献类型：
--
作者：
H. Noguchi;K. Nomura;K. Abe;S. Fujita;Eishi Arima;Kyundong Kim;Takashi Nakada;Shinobu Miwa;Hiroshi Nakamura
本文提出了一种利用新型DRAM/MRAM单元级混合结构存储器(D-MRAM)的非易失性高速缓存结构，该结构能够在不增加面积开销的情况下有效地降低高性能移动SoC的功耗。这里，降低有功功率的关键是DRAM模式的间歇刷新过程。与传统的SRAM相比，D-MRAM在降低静态功耗方面具有优势，因为在D-MRAM单元中没有静态漏路径，并且在用作MRAM模式时不需要向其单元提供电压。此外，由于采用了先进的垂直磁隧道结(p-MTJ)，在不缩短保留时间的情况下降低了写入能量和延迟，D-MRAM能够通过取代传统的SRAM缓存来降低功耗。考虑到65 nm的CMOS工艺，1MB存储器宏在DRAM模式下的读写延迟为2.2 ns/1.5 ns，在MRAM模式下为2.2 ns/4.5 ns，而在SRAM模式下为1.17 ns。SPEC CPU2006基准测试显示，总高速缓冲存储器的每指令能量(EPI)平均可显著降低71%，而D-MRAM高速缓冲存储器体系结构的每周期指令(IPC)性能平均仅下降约4%，尽管其延迟开销。
This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce static power consumptions compared to the conventional SRAM, because there are no static leakage paths in the D-MRAM cell and it is not needed to supply voltage to its cells when used as the MRAM-mode. Besides, with advanced perpendicular magnetic tunnel junctions (p-MTJ), which decreases the write energy and latency without shortening its retention time, D-MRAM is capable of power reduction by replacing the traditional SRAM caches. Considering the 65-nm CMOS technology, the access latencies of 1MB memory macro are 2.2 ns / 1.5 ns for read / write in DRAM mode, and 2.2 ns / 4.5 ns in MRAM mode, while those of SRAM are 1.17 ns. The SPEC CPU2006 benchmarks have revealed that the energy per instruction (EPI) of the total cache memory can be dramatically reduced by 71 % on average, and the instruction per cycle (IPC) performance of the D-MRAM cache architecture degraded only by approximately 4 % on average in spite of its latency overhead.