A random access analog memory with master-slave structure for implementing hexadecimal logic
A random access analog memory with master-slave structure for implementing hexadecimal logic
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DOI：
10.1109/socc.2017.8225995
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发表时间：
2017-09
期刊：
影响因子：
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通讯作者：
Renyuan Zhang;M. Kaneko
中科院分区：
文献类型：
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作者：
Renyuan Zhang;M. Kaneko
在这项工作中，设计了随机访问模拟内存，而无需静态功率。模拟记忆似乎是互连大大减少的好处，但受到静态功耗和不准确的影响。作为混合动力，本文针对的十六进制信号处理是针对的。为了存储十六进制值，即使实现了十六进制顺序逻辑，提出了一个主奴隶结构，该结构是用十八个晶体管提出的，这是四个二进制二进制主奴隶flipflop的28％。十六进制电压值存储在浮闸上；并且读出操作由比较器执行，以保护存储的电压。该比较器仅在读出操作期间提供动力。通过这种方式，消除了静电功率。通过使用所提出的时序控制模式，主阶段是为十六进制顺序逻辑而组织的。作为演示，根据提出的模拟记忆而没有组合逻辑电路，设计了16个点，其中设备数量与二进制方法相比减少。从电路仿真结果中，设计的电路保持十六进制值并正确执行十六进制函数。
A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is proposed with eighteen transistors, which is 28% of four pieces of binary master-slave flipflop. The hexadecimal voltage values are stored on the floating gate; and the read-out operations are executed by a comparator to protect the stored voltage. This comparator is powered only during the read-out operation. In this manner, the static power is eliminated. By using the proposed timing control mode, the master and slave stages are organized for hexadecimal sequential logic. As a demonstration, a sixteen-counter is designed on the basis of proposed analog memory without combinational logic circuits, in which the number of devices is reduced in contrast of binary approaches. From the circuit simulation results, the designed circuits maintain the hexadecimal values and execute hexadecimal functions correctly.