Low-frequency noise reduction technique for accelerometer readout circuit
Low-frequency noise reduction technique for accelerometer readout circuit
复制标题
加速度计读出电路的低频降噪技术
DOI：
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复制
发表时间：
2016
期刊：
影响因子：
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通讯作者：
Y. Juang
中科院分区：
文献类型：
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作者：
Po;C. Yeh;H. Tsai;Y. Juang
提出了一种用于电容式加速度计读出电路的随机斩波器结构。这种技术使低频闪烁噪声随机化，使其更像热噪声，并且还由于加速而增加了小信号电荷。与传统的相关双采样（CDS）方法相比，所提出的RC读出电路的噪声等效加速度（NEA）大大降低。所提出的方法还消除了在CDS减法阶段的长传播路径。这有利于读出电路的运算放大器（OTA）设计的操作速度和功耗。HSPICE©瞬态噪声仿真结果表明，所提出的RC结构可以达到75 μg/rtHz的NEA，同时将功耗降低到6 μA。这种低功耗和低噪声特性使该RC加速度计适用于可穿戴应用。
This paper proposed a random chopper (RC) architecture for use in a capacitive accelerometer readout circuit. This technique randomizes low-frequency flicker noise to be more thermal-noise-like, and also boosts the small signal charges due to acceleration. The noise-equivalent acceleration (NEA) of the proposed RC readout circuit is greatly reduced compared with conventional correlated double sampling (CDS) approaches. The proposed method also eliminates the long propagating path during the CDS subtraction phase. This benefits the operation speed and power consumption of the operational transconductance amplifier (OTA) design of the readout circuit. The HSPICE© transient noise simulation results shows that the proposed RC architecture can reach 75 μg/rtHz NEA while reducing the current consumption to 6 μA. This low-power and low-noise features make this RC accelerometer suitable for wearable applications.