A Resistive Random Access Memory Addon for the NCSU FreePDK 45 nm
A Resistive Random Access Memory Addon for the NCSU FreePDK 45 nm
复制标题
适用于 NCSU FreePDK 45 nm 的电阻式随机存取存储器插件
DOI：
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发表时间：
2019
影响因子：
2.4
通讯作者：
P. Gaillardon
中科院分区：
文献类型：
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作者：
Edouard Giacomin;P. Gaillardon
在过去的几年里，阻性随机存取存储器（RRAM）已被广泛研究用于大量应用（神经形态计算、非易失性数字设计、内存中计算等）这是因为其具有诸如高速操作、非易失性保持和低功耗等有前途的特性。因此，已经提出了许多SPICE RRAM模型以允许适当的电路级仿真。然而，当涉及到全定制的基于RRAM的布局和电子设计自动化验证时，物理设计是一个问题，因为没有基于RRAM的工艺设计套件是公开可用的。因此，在电路和芯片级评估基于RRAM的系统在面积方面的益处和度量是一个问题。实际上，许多基于RRAM的系统面积结果仅基于RRAM和晶体管器件计数，而不是基于确切的布局面积，这可能导致不准确的结果。在本文中，我们提出了一个插件描述CMOS兼容RRAM技术，NCSU FreePDK 45 nm。该插件由斯坦福大学RRAM Verilog-A模型组成，该模型适合已发表的实验结果，以及一组设计规则检查和布局与原理图规则，以确保Calibre的物理设计的正确性。我们通过三个案例研究表明，准确的基于RRAM的系统面积评估，可以在电路和芯片级的建议插件的好处。
During the past few years, resistive random access memory (RRAM) have been widely studied for a large set of applications (neuromorphic computing, nonvolatile digital design, in-memory computation, etc.) due to its promising characteristics such as high-speed operations, nonvolatile retention, and low-power consumption. As a result, many SPICE RRAM models have been proposed to allow proper circuit-level simulations. However, physical design is a problem when it comes to full-custom RRAM-based layout and electronic design automation verification since no RRAM-based process design kits are publicly available. Consequently, evaluating the benefits and the metrics of RRAM-based systems at the circuit and chip levels in term of area is an issue. Indeed, many RRAM-based systems area results are based solely on the RRAM and transistor device count and not on the exact layout area, potentially leading to inaccurate results. In this paper, we propose an addon describing a CMOS compatible RRAM technology, for the NCSU FreePDK 45 nm. The addon comprises of the Stanford RRAM Verilog-A model, fitted on published experimental results as well as a set of design rule check and layout versus schematic rules for Calibre to ensure the correctness of the physical designs. We demonstrate the benefits of the proposed addon through three case studies to show that accurate RRAM-based systems area evaluations can be obtained at both circuit and chip levels.