Effects of Basal Plane Dislocation Density in 4H-SiC Substrate on Degradation of Body-Diode Forward Voltage
Effects of Basal Plane Dislocation Density in 4H-SiC Substrate on Degradation of Body-Diode Forward Voltage
复制标题
4H-SiC 衬底中基面位错密度对体二极管正向电压降低的影响
DOI：
--
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
K. Fukuda
中科院分区：
文献类型：
--
作者：
Naoyuki Kawabata;A. Tanaka;M. Tsujimura;Y. Ueji;K. Omote;H. Yamaguchi;H. Matsuhata;K. Fukuda
研究了4 H-碳化硅（SiC）衬底中基面位错（BPD）密度对体二极管正向电压（Vsd）退化的影响。使用反射X射线形貌术，在制造金属氧化物半导体场效应晶体管（MOSFET）之前从衬底自动估计BPD密度。在Vsd位移（其由在160 A/cm 2下正向偏压应力约500小时前后的差异计算）与基板的BPD密度之间发现强正相关性。我们表明，它是可能的预测Vsd的变化，从SiC衬底的BPD密度之前，MOSFET的制造。此外，我们研究了堆垛层错（SFs）的起源作为一个结果的应用程序的正向偏置应力。我们推测，SF是由BPD转换为线程刃位错在epi/sub界面，以及由BPD渗透到外延层。
We investigated the effect of the basal plane dislocation (BPD) density in 4H-silicon carbide (SiC) substrates on the forward voltage (Vsd) degradation of body-diodes. Using reflection X-ray topography, the BPD density was automatically estimated from the substrates prior to fabrication of metal–oxide–semiconductor field-effect transistors (MOSFETs). A strong positive correlation was found between the Vsd shift, which was calculated from the difference before and after forward bias stress at 160 A/cm2 for ~500 hours, and the BPD density of the substrate. We show that it is possible to predict Vsd shifts from the BPD densities of SiC substrates prior to the fabrication of MOSFETs. In addition, we examined the origin of stacking faults (SFs) as a result of the application of forward bias stress. We presume that SFs are formed by BPDs converted to threading edge dislocations at the epi/sub interface, as well as by BPDs penetrating into the epitaxial layer.