Binary-coded decimal digit multipliers
Binary-coded decimal digit multipliers
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DOI：
10.1049/iet-cdt:20060160
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发表时间：
2007-07
期刊：
影响因子：
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通讯作者：
G. Jaberipur;Amir Kaivani
中科院分区：
文献类型：
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作者：
G. Jaberipur;Amir Kaivani
随着十进制计算机算术在科学、商业、金融和基于互联网的应用中的日益普及，十进制算术算法的硬件实现变得越来越重要。硬件十进制算术单元现在用作一些最近商业化的通用处理器的组成部分，其中复杂的十进制算术运算（例如乘法）已经通过相当慢的迭代硬件算法来实现。然而，随着超大规模集成电路（VLSI）技术的快速发展，半并行和全并行硬件十进制乘法单元有望很快发展起来。十进制数字的主要表示是二进制编码的十进制（BCD）编码。BCD数字乘法器可以作为十进制乘法器的关键构建块，而不管并行度如何。BCD数字乘法器从两个输入BCD数字产生两个BCD数字乘积。我们为后者提供了一种新颖的设计，在BCD乘法器实现中显示出一些优势。
With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi- and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations.