A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS
A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS
复制标题
使用斯坦福超低功耗 CMOS 的 200 mV 自测试编码器/解码器
DOI：
10.1109/isscc.1994.344717
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
J. Shott
中科院分区：
文献类型：
--
作者：
J. Burr;J. Shott
CMOS测试芯片包括一个1 k晶体管自测编码器/解码器，可验证在低至200 mV的电源电压下无错误，实现了标准5 V CMOS的1/625功率延迟积。该电路的最大无误差工作频率作为电源和阈值电压的函数，在这里报告和电压缩放的性能与环形振荡器的数据相比，报告较早。即使晶体管的主体相对于源极正向偏置以诱导/spl sim/100 mV耗尽模式阈值，电路也能工作。<<ETX>>
A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS. The maximum error-free operating frequency of this circuit as a function of supply and threshold voltage is reported here and voltage scaling of performance is compared with ring-oscillator data reported earlier. The circuit works even when bodies of transistors are forward-biased relative to sources to induce /spl sim/100mV depletion-mode thresholds.<<ETX>>