Fabrication of metallic single electron transistors featuring plasma enhanced atomic layer deposition of tunnel barriers
Fabrication of metallic single electron transistors featuring plasma enhanced atomic layer deposition of tunnel barriers
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采用等离子体增强隧道势垒原子层沉积的金属单电子晶体管的制造
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
G. Karbasian
中科院分区：
文献类型：
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作者：
G. Karbasian
随着集成电路（IC）中器件密度的不断增加，每单位面积的功耗也越来越高，因此电路中的温度也越来越高。由于温度会影响电路的性能和可靠性，因此使逻辑器件的能耗最小化是现在关注的焦点。根据国际半导体技术路线图（ITRS），单电子晶体管（SET）有望实现任何已知逻辑器件的最低功耗，每个开关事件低至1×10 J。此外，SET是迄今为止最灵敏的静电计，并且能够检测电子电荷的一部分。尽管它们的低功耗和电荷检测的高灵敏度，这些设备的室温操作是相当具有挑战性的，主要是由于在制造所需的尺寸小于10 nm的结构的光刻约束。硅基SET已被报道在室温下工作。
by Golnaz Karbasian The continuing increase of the device density in integrated circuits (ICs) gives rise to the high level of power that is dissipated per unit area and consequently a high temperature in the circuits. Since temperature affects the performance and reliability of the circuits, minimization of the energy consumption in logic devices is now the center of attention. According to the International Technology Roadmaps for Semiconductors (ITRS), single electron transistors (SETs) hold the promise of achieving the lowest power of any known logic device, as low as 1×10 J per switching event. Moreover, SETs are the most sensitive electrometers to date, and are capable of detecting a fraction of an electron charge. Despite their low power consumption and high sensitivity for charge detection, room temperature operation of these devices is quite challenging mainly due to lithographical constraints in fabricating structures with the required dimensions of less than 10 nm. Silicon based SETs have been reported to operate at room temperature.