Quantum circuit physical design flow for 2D nearest‐neighbor architectures
Quantum circuit physical design flow for 2D nearest‐neighbor architectures
复制标题
二维最近邻架构的量子电路物理设计流程
DOI：
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发表时间：
2017
影响因子：
2.3
通讯作者：
N. Mohammadzadeh
中科院分区：
文献类型：
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作者：
Azim Farghadan;N. Mohammadzadeh
物理设计过程采用由逻辑综合过程生成的网表，并将网表放置在物理平台上并对其进行布线。在某些物理平台中，物理量子位必须放置在2D网格上。网格的每个节点代表一个量子比特。在这些平台中，在非相邻量子位上执行量子门非常容易出错或难以控制。因此，量子门被限制为在相邻的量子比特上执行。如果逻辑电路中的量子位不相邻，则需要构造交换门的通信通道。用于在网格上映射量子位的算法在减少交换门的数量从而减少电路延迟方面具有重要作用。针对这一问题，本文提出了一种基于二维网格的量子电路物理设计流程。它包含三种算法，用于查找量子位放置，物理量子位放置和路由的顺序。仿真结果表明，与文献中的最佳方案相比，该流程不仅使交换门的平均数量减少了约16%，而且平均运行时间也提高了约94%。Copyright © 2017 John Wiley & Sons，Ltd.
The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd.